// Copyright (C) 1953-2020 NUDT
// Verilog module name - tester_4_0_top 
// Version: V1.0
// Created:
//         by - fenglin 
//         at - 8.2022
////////////////////////////////////////////////////////////////////////////
// Description:
//         tester of top module 
//            
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module tester_4_0_top
(
       i_core_clk,
       i_rst_n,

	   i_gmii_rxclk_p0,
	   i_gmii_rxdv_p0,
	   iv_gmii_rxd_p0,
	   i_gmii_rxer_p0,            
	   ov_gmii_txd_p0,
	   o_gmii_txen_p0,
	   o_gmii_txer_p0,
	   o_gmii_txclk_p0,  
       
	   i_gmii_rxclk_p1,
	   i_gmii_rxdv_p1,
	   iv_gmii_rxd_p1,
	   i_gmii_rxer_p1,            
	   ov_gmii_txd_p1,
	   o_gmii_txen_p1,
	   o_gmii_txer_p1,
	   o_gmii_txclk_p1,  
       
	   i_gmii_rxclk_p2,
	   i_gmii_rxdv_p2,
	   iv_gmii_rxd_p2,
	   i_gmii_rxer_p2,            
	   ov_gmii_txd_p2,
	   o_gmii_txen_p2,
	   o_gmii_txer_p2,
	   o_gmii_txclk_p2,         
              
	   i_gmii_rxclk_p3,
	   i_gmii_rxdv_p3,
	   iv_gmii_rxd_p3,
	   i_gmii_rxer_p3,            
	   ov_gmii_txd_p3,
	   o_gmii_txen_p3,
	   o_gmii_txer_p3,
	   o_gmii_txclk_p3,

       ov_cfg_finish,
       o_s_pulse    ,
       o_cycle_start       
);

input  	            i_core_clk;
input  	            i_rst_n;

input  	            i_gmii_rxclk_p0;
input  	            i_gmii_rxdv_p0;
input  	   [7:0]    iv_gmii_rxd_p0;
input  	            i_gmii_rxer_p0;            
output     [7:0]    ov_gmii_txd_p0;
output    	        o_gmii_txen_p0;
output    	        o_gmii_txer_p0;
output    	        o_gmii_txclk_p0; 

input  	            i_gmii_rxclk_p1;
input  	            i_gmii_rxdv_p1;
input  	   [7:0]    iv_gmii_rxd_p1;
input  	            i_gmii_rxer_p1;            
output     [7:0]    ov_gmii_txd_p1;
output    	        o_gmii_txen_p1;
output    	        o_gmii_txer_p1;
output    	        o_gmii_txclk_p1; 

input  	            i_gmii_rxclk_p2;
input  	            i_gmii_rxdv_p2;
input  	   [7:0]    iv_gmii_rxd_p2;
input  	            i_gmii_rxer_p2;            
output     [7:0]    ov_gmii_txd_p2;
output    	        o_gmii_txen_p2;
output    	        o_gmii_txer_p2;
output   	        o_gmii_txclk_p2; 

input  	            i_gmii_rxclk_p3;
input  	            i_gmii_rxdv_p3;
input  	   [7:0]    iv_gmii_rxd_p3;
input  	            i_gmii_rxer_p3;            
output     [7:0]    ov_gmii_txd_p3;
output    	        o_gmii_txen_p3;
output    	        o_gmii_txer_p3;
output    	        o_gmii_txclk_p3; 

output              o_cycle_start;
output     [1:0]    ov_cfg_finish;
output reg          o_s_pulse    ;
//adp2tsnchip 
wire				w_gmii_dv_p1_adp2tsnchip;
wire	[7:0]		wv_gmii_rxd_p1_adp2tsnchip;
wire				w_gmii_er_p1_adp2tsnchip;

wire				w_gmii_dv_p2_adp2tsnchip;
wire	[7:0]		wv_gmii_rxd_p2_adp2tsnchip;
wire				w_gmii_er_p2_adp2tsnchip;

wire				w_gmii_dv_p3_adp2tsnchip;
wire	[7:0]		wv_gmii_rxd_p3_adp2tsnchip;
wire				w_gmii_er_p3_adp2tsnchip;
//tsnchip2adp      
wire    [7:0] 	    wv_gmii_txd_p1_tsnchip2adp;
wire    		 	w_gmii_tx_en_p1_tsnchip2adp;
wire    		 	w_gmii_tx_er_p1_tsnchip2adp;
        
wire    [7:0] 	    wv_gmii_txd_p2_tsnchip2adp;
wire    		 	w_gmii_tx_en_p2_tsnchip2adp;
wire    		 	w_gmii_tx_er_p2_tsnchip2adp;

wire    [7:0] 	    wv_gmii_txd_p3_tsnchip2adp;
wire    		 	w_gmii_tx_en_p3_tsnchip2adp;
wire    		 	w_gmii_tx_er_p3_tsnchip2adp;
//p1_rx to um
wire    [133:0]     wv_data_iip12um;
wire			    w_data_wr_iip12um;
wire	            w_fifo_overflow_pulse_iip12um;
wire	            w_fifo_underflow_pulse_iip12um;
//p2_rx to um
wire    [133:0]     wv_data_iip22um;
wire			    w_data_wr_iip22um;
wire	            w_fifo_overflow_pulse_iip22um;
wire	            w_fifo_underflow_pulse_iip22um;
//p3_rx to um
wire    [133:0]     wv_data_iip32um;
wire			    w_data_wr_iip32um;
wire	            w_fifo_overflow_pulse_iip32um;
wire	            w_fifo_underflow_pulse_iip32um;
//um to p0/p1/p2/p3 rx
wire    [63:0]      wv_local_cnt_tim2other;
wire                w_local_cnt_rst_hcp2osm;
wire    [79:0]      wv_syn_clk_hcp2other   ;
//wire  [31:0]      wv_syn_clock_cycle_stc2tss   ;
//um to port
wire    [133:0]     wv_data_um2p1;
wire    	        w_data_um2p1_wr;
wire    [6:0]       wv_fifo_usedw_p12um;
                    
wire    [133:0]     wv_data_um2p2;
wire    	        w_data_um2p2_wr;
wire    [6:0]       wv_fifo_usedw_p22um;
                    
wire    [133:0]     wv_data_um2p3;
wire    	        w_data_um2p3_wr;
wire    [6:0]       wv_fifo_usedw_p32um;

wire                w_data_wr_p0_osm2hcp   ; 
wire    [8:0]	    wv_data_p0_osm2hcp ; 
wire    [8:0]       wv_data_p0_hcp2osm ; 
wire    	        w_data_wr_p0_hcp2osm;

wire                w_data_wr_p1_iop2osm   ;
wire    [8:0]       wv_data_p1_iop2osm     ;  
wire                w_data_ready_p1_osm2iop; 
wire                w_data_wr_p1_osm2iip   ;
wire    [8:0]       wv_data_p1_osm2iip     ;

wire                w_data_wr_p2_iop2osm   ;
wire    [8:0]       wv_data_p2_iop2osm     ;  
wire                w_data_ready_p2_osm2iop; 
wire                w_data_wr_p2_osm2iip   ;
wire    [8:0]       wv_data_p2_osm2iip     ;

wire                w_data_wr_p3_iop2osm   ;
wire    [8:0]       wv_data_p3_iop2osm     ;  
wire                w_data_ready_p3_osm2iop; 
wire                w_data_wr_p3_osm2iip   ;
wire    [8:0]       wv_data_p3_osm2iip     ;

wire                w_wr_hcp2osm         ;
wire    [31:0]      wv_wdata_hcp2osm     ;
wire    [18:0]      wv_addr_hcp2osm      ;
wire                w_addr_fixed_hcp2osm ;
wire                w_rd_hcp2osm         ;
wire                w_wr_osm2hcp         ;
wire    [31:0]      wv_rdata_osm2hcp     ;
wire    [18:0]      wv_raddr_osm2hcp     ;
wire                w_addr_fixed_osm2hcp ;

wire    [9:0]       wv_time_slot        ;
wire    [10:0]      wv_time_slot_length ;
wire    [10:0]      wv_schedule_period  ;
wire                w_time_slot_switch  ;
wire                w_tsn_or_tte_hcp2osm;

wire                w_rc_rxenable_hcp2tss;
wire                w_st_rxenable_hcp2tss;

wire    [11:0]      wv_hcp_mid_hcp2tse   ;

wire    [65:0]      wv_command_hcp2hub        ;   
wire                w_command_wr_hcp2hub      ; 
wire    [65:0]      wv_command_ack_hub2hcp    ;
wire                w_command_ack_wr_hub2hcp  ; 

wire    [63:0]      wv_command_hub2tse        ;  
wire                w_command_wr_hub2tse      ;
wire    [63:0]      wv_command_tse2hub        ;
wire                w_command_wr_tse2hub      ;

wire    [63:0]      wv_command_hub2osm_0      ;
wire                w_command_wr_hub2osm_0    ;
wire    [63:0]      wv_command_osm2hub_0      ;
wire                w_command_wr_osm2hub_0    ;

wire    [63:0]      wv_command_hub2osm_1      ;
wire                w_command_wr_hub2osm_1    ;
wire    [63:0]      wv_command_osm2hub_1      ;
wire                w_command_wr_osm2hub_1    ;

wire    [63:0]      wv_command_hub2osm_2      ;
wire                w_command_wr_hub2osm_2    ;
wire    [63:0]      wv_command_osm2hub_2      ;
wire                w_command_wr_osm2hub_2    ;

wire    [63:0]      wv_command_hub2osm_3      ;
wire                w_command_wr_hub2osm_3    ;
wire    [63:0]      wv_command_osm2hub_3      ;
wire                w_command_wr_osm2hub_3    ;

wire    [18:0]      wv_addr_cit2all       ;
wire    [31:0]      wv_wdata_cit2all      ;
wire                w_addr_fixed_cit2all  ;
wire                w_wr_cit2grm          ;
wire                w_rd_cit2grm          ;
wire                w_wr_grm2cit          ;
wire    [18:0]      wv_addr_grm2cit       ;
wire                w_addr_fixed_grm2cit  ;
wire    [31:0]      wv_rdata_grm2cit      ;

wire                w_osm_req_tx_pulse_p0_osm2hcp   ;
wire                w_osm_resp_rx_pulse_p0_osm2hcp  ;
wire                w_osm_req_tx_pulse_p1_osm2hcp   ;
wire                w_osm_resp_rx_pulse_p1_osm2hcp  ;
wire                w_osm_req_tx_pulse_p2_osm2hcp   ;
wire                w_osm_resp_rx_pulse_p2_osm2hcp  ;
wire                w_osm_req_tx_pulse_p3_osm2hcp   ;
wire                w_osm_resp_rx_pulse_p3_osm2hcp  ;

wire                w_osm_req_rx_pulse_p0_osm2hcp   ;
wire                w_osm_resp_tx_pulse_p0_osm2hcp  ;
wire                w_osm_req_rx_pulse_p1_osm2hcp   ;
wire                w_osm_resp_tx_pulse_p1_osm2hcp  ;
wire                w_osm_req_rx_pulse_p2_osm2hcp   ;
wire                w_osm_resp_tx_pulse_p2_osm2hcp  ;
wire                w_osm_req_rx_pulse_p3_osm2hcp   ;
wire                w_osm_resp_tx_pulse_p3_osm2hcp  ;

assign o_gmii_txclk_p0 = i_gmii_rxclk_p0;
assign o_gmii_txclk_p1 = i_gmii_rxclk_p1;
assign o_gmii_txclk_p2 = i_gmii_rxclk_p2;
assign o_gmii_txclk_p3 = i_gmii_rxclk_p3;

wire                  w_core_rst_n;
wire                  w_gmii_rst_n_p0;
wire                  w_gmii_rst_n_p1;
wire                  w_gmii_rst_n_p2;
wire                  w_gmii_rst_n_p3;

assign ov_cfg_finish = {w_st_rxenable_hcp2tss,w_rc_rxenable_hcp2tss};

reg   r_s_data;
always@(posedge i_core_clk or negedge w_core_rst_n)begin 
    if(!w_core_rst_n) begin
		o_s_pulse          <= 1'b0;
		r_s_data           <= 1'b0;
    end
    else begin
	    r_s_data <= wv_syn_clk_hcp2other[32];
	    if(r_s_data != wv_syn_clk_hcp2other[32])begin
            o_s_pulse          <= 1'b1;
        end	
        else begin
            o_s_pulse          <= 1'b0;
        end		
	end
end
hardware_control_point hardware_control_point_inst(
.i_clk                            (i_core_clk                ),
.i_rst_n                          (w_core_rst_n              ),  

.i_tsnnic_or_tsnswitch            (1'b1                      ),//1:tsnnic.  0:tsnswitch
.ov_syn_clk                       (wv_syn_clk_hcp2other                ),
.o_local_cnt_rst                  (w_local_cnt_rst_hcp2osm   ),
.o_tsn_or_tte                     (w_tsn_or_tte_hcp2osm      ),

//.i_gmii_rxclk_from_cpu            (i_clk ),
//.i_gmii_rx_dv_from_cpu            (1'b0  ), 
//.iv_gmii_rxd_from_cpu             (8'b0  ),
//.i_gmii_rx_er_from_cpu            (1'b0  ),
//.ov_gmii_txd_to_cpu               (    ),
//.o_gmii_tx_en_to_cpu              (    ),
//.o_gmii_txclk_to_cpu              (    ),
//.o_gmii_tx_er_to_cpu              (    ),

.iv_data_cpu                        (9'b0),
.i_data_wr_cpu                      (1'b0),
.ov_data_cpu                        (),
.o_data_wr_cpu                      (),

.i_data_wr_from_tss               (w_data_wr_p0_osm2hcp      ),
.iv_data_from_tss                 (wv_data_p0_osm2hcp        ),   
.ov_data_to_tss                   (wv_data_p0_hcp2osm        ),   
.o_data_wr_to_tss                 (w_data_wr_p0_hcp2osm      ), 

.iv_data_tap                      (9'b0                      ),
.i_data_wr_tap                    (1'b0                      ),

.ov_local_id                      (wv_hcp_mid_hcp2tse        ), 
.iv_tss_ver                       (32'b0                     ),
.o_rc_rxenable                    (w_rc_rxenable_hcp2tss ),
.o_st_rxenable                    (w_st_rxenable_hcp2tss ),

.i_tsmp_lookup_table_key_wr       (1'b0                  ),
.iv_tsmp_lookup_table_key         (48'b0                 ),
.ov_tsmp_lookup_table_outport     (                      ),
.o_tsmp_lookup_table_outport_wr   (                      ),

.o_cycle_start                    (o_cycle_start         ),
.o_sync_ok                        (                      ),

.ov_hcp_ext_command               (wv_command_hcp2hub                    ),
.o_hcp_ext_command_wr             (w_command_wr_hcp2hub                  ),        
.iv_hcp_ext_command_ack           (wv_command_ack_hub2hcp                ),
.i_hcp_ext_command_ack_wr         (w_command_ack_wr_hub2hcp              ),

.i_osm_req_tx_pulse_p0            (w_osm_req_tx_pulse_p0_osm2hcp  ),     
.i_osm_resp_rx_pulse_p0           (w_osm_resp_rx_pulse_p0_osm2hcp ),     
.i_osm_req_tx_pulse_p1            (w_osm_req_tx_pulse_p1_osm2hcp  ),     
.i_osm_resp_rx_pulse_p1           (w_osm_resp_rx_pulse_p1_osm2hcp ),     
.i_osm_req_tx_pulse_p2            (w_osm_req_tx_pulse_p2_osm2hcp  ),     
.i_osm_resp_rx_pulse_p2           (w_osm_resp_rx_pulse_p2_osm2hcp ),     
.i_osm_req_tx_pulse_p3            (w_osm_req_tx_pulse_p3_osm2hcp  ),     
.i_osm_resp_rx_pulse_p3           (w_osm_resp_rx_pulse_p3_osm2hcp ),     
.i_osm_req_tx_pulse_p4            (1'b0),//(w_osm_req_tx_pulse_p4_osm2hcp  ),     
.i_osm_resp_rx_pulse_p4           (1'b0),//(w_osm_resp_rx_pulse_p4_osm2hcp ),     
.i_osm_req_tx_pulse_p5            (1'b0),//(w_osm_req_tx_pulse_p5_osm2hcp  ),     
.i_osm_resp_rx_pulse_p5           (1'b0),//(w_osm_resp_rx_pulse_p5_osm2hcp ),     
.i_osm_req_tx_pulse_p6            (1'b0),//(w_osm_req_tx_pulse_p6_osm2hcp  ),     
.i_osm_resp_rx_pulse_p6           (1'b0),//(w_osm_resp_rx_pulse_p6_osm2hcp ),     
.i_osm_req_tx_pulse_p7            (1'b0),//(w_osm_req_tx_pulse_p7_osm2hcp  ),     
.i_osm_resp_rx_pulse_p7           (1'b0),//(w_osm_resp_rx_pulse_p7_osm2hcp ),     
.i_osm_req_tx_pulse_p8            (1'b0),//(w_osm_req_tx_pulse_p8_osm2hcp  ),     
.i_osm_resp_rx_pulse_p8           (1'b0),//(w_osm_resp_rx_pulse_p8_osm2hcp ),     
.i_osm_req_tx_pulse_p9            (1'b0),//(w_osm_req_tx_pulse_p9_osm2hcp  ),     
.i_osm_resp_rx_pulse_p9           (1'b0),//(w_osm_resp_rx_pulse_p9_osm2hcp ),     
.i_osm_req_tx_pulse_p10           (1'b0),//(w_osm_req_tx_pulse_p10_osm2hcp ),     
.i_osm_resp_rx_pulse_p10          (1'b0),//(w_osm_resp_rx_pulse_p10_osm2hcp),     
.i_osm_req_tx_pulse_p11           (1'b0),//(w_osm_req_tx_pulse_p11_osm2hcp ),     
.i_osm_resp_rx_pulse_p11          (1'b0),//(w_osm_resp_rx_pulse_p11_osm2hcp),     
.i_osm_req_tx_pulse_p12           (1'b0),//(w_osm_req_tx_pulse_p12_osm2hcp ),     
.i_osm_resp_rx_pulse_p12          (1'b0),//(w_osm_resp_rx_pulse_p12_osm2hcp),     
.i_osm_req_tx_pulse_p13           (1'b0),//(w_osm_req_tx_pulse_p13_osm2hcp ),     
.i_osm_resp_rx_pulse_p13          (1'b0),//(w_osm_resp_rx_pulse_p13_osm2hcp),     
.i_osm_req_tx_pulse_p14           (1'b0),//(w_osm_req_tx_pulse_p14_osm2hcp ),     
.i_osm_resp_rx_pulse_p14          (1'b0),//(w_osm_resp_rx_pulse_p14_osm2hcp),     
.i_osm_req_tx_pulse_p15           (1'b0),//(w_osm_req_tx_pulse_p15_osm2hcp ),     
.i_osm_resp_rx_pulse_p15          (1'b0),//(w_osm_resp_rx_pulse_p15_osm2hcp),     
.i_osm_req_tx_pulse_p16           (1'b0),//(w_osm_req_tx_pulse_p16_osm2hcp ),     
.i_osm_resp_rx_pulse_p16          (1'b0),//(w_osm_resp_rx_pulse_p16_osm2hcp),     
.i_osm_req_tx_pulse_p17           (1'b0),//(w_osm_req_tx_pulse_p17_osm2hcp ),     
.i_osm_resp_rx_pulse_p17          (1'b0),//(w_osm_resp_rx_pulse_p17_osm2hcp),     
.i_osm_req_tx_pulse_p18           (1'b0),//(w_osm_req_tx_pulse_p18_osm2hcp ),     
.i_osm_resp_rx_pulse_p18          (1'b0),//(w_osm_resp_rx_pulse_p18_osm2hcp),     
.i_osm_req_tx_pulse_p19           (1'b0),//(w_osm_req_tx_pulse_p19_osm2hcp ),     
.i_osm_resp_rx_pulse_p19          (1'b0),//(w_osm_resp_rx_pulse_p19_osm2hcp),     
.i_osm_req_tx_pulse_p20           (1'b0),//(w_osm_req_tx_pulse_p20_osm2hcp ),     
.i_osm_resp_rx_pulse_p20          (1'b0),//(w_osm_resp_rx_pulse_p20_osm2hcp),     
.i_osm_req_tx_pulse_p21           (1'b0),//(w_osm_req_tx_pulse_p21_osm2hcp ),     
.i_osm_resp_rx_pulse_p21          (1'b0),//(w_osm_resp_rx_pulse_p21_osm2hcp),     
.i_osm_req_tx_pulse_p22           (1'b0),//(w_osm_req_tx_pulse_p22_osm2hcp ),     
.i_osm_resp_rx_pulse_p22          (1'b0),//(w_osm_resp_rx_pulse_p22_osm2hcp),     
.i_osm_req_tx_pulse_p23           (1'b0),//(w_osm_req_tx_pulse_p23_osm2hcp ),     
.i_osm_resp_rx_pulse_p23          (1'b0),//(w_osm_resp_rx_pulse_p23_osm2hcp),     
.i_osm_req_tx_pulse_p24           (1'b0),//(w_osm_req_tx_pulse_p24_osm2hcp ),     
.i_osm_resp_rx_pulse_p24          (1'b0),//(w_osm_resp_rx_pulse_p24_osm2hcp),     
.i_osm_req_tx_pulse_p25           (1'b0),//(w_osm_req_tx_pulse_p25_osm2hcp ),     
.i_osm_resp_rx_pulse_p25          (1'b0),//(w_osm_resp_rx_pulse_p25_osm2hcp),     
.i_osm_req_tx_pulse_p26           (1'b0),//(w_osm_req_tx_pulse_p26_osm2hcp ),     
.i_osm_resp_rx_pulse_p26          (1'b0),//(w_osm_resp_rx_pulse_p26_osm2hcp),     
.i_osm_req_tx_pulse_p27           (1'b0),//(w_osm_req_tx_pulse_p27_osm2hcp ),     
.i_osm_resp_rx_pulse_p27          (1'b0),//(w_osm_resp_rx_pulse_p27_osm2hcp),     
.i_osm_req_tx_pulse_p28           (1'b0),//(w_osm_req_tx_pulse_p28_osm2hcp ),     
.i_osm_resp_rx_pulse_p28          (1'b0),//(w_osm_resp_rx_pulse_p28_osm2hcp),     
.i_osm_req_tx_pulse_p29           (1'b0),//(w_osm_req_tx_pulse_p29_osm2hcp ),     
.i_osm_resp_rx_pulse_p29          (1'b0),//(w_osm_resp_rx_pulse_p29_osm2hcp),     
.i_osm_req_tx_pulse_p30           (1'b0),//(w_osm_req_tx_pulse_p30_osm2hcp ),     
.i_osm_resp_rx_pulse_p30          (1'b0),//(w_osm_resp_rx_pulse_p30_osm2hcp),     
.i_osm_req_tx_pulse_p31           (1'b0),//(w_osm_req_tx_pulse_p31_osm2hcp ),     
.i_osm_resp_rx_pulse_p31          (1'b0),//(w_osm_resp_rx_pulse_p31_osm2hcp), 
                              
.i_osm_req_rx_pulse_p0            (w_osm_req_rx_pulse_p0_osm2hcp  ),
.i_osm_resp_tx_pulse_p0           (w_osm_resp_tx_pulse_p0_osm2hcp ),
.i_osm_req_rx_pulse_p1            (w_osm_req_rx_pulse_p1_osm2hcp  ),
.i_osm_resp_tx_pulse_p1           (w_osm_resp_tx_pulse_p1_osm2hcp ),
.i_osm_req_rx_pulse_p2            (w_osm_req_rx_pulse_p2_osm2hcp  ),
.i_osm_resp_tx_pulse_p2           (w_osm_resp_tx_pulse_p2_osm2hcp ),
.i_osm_req_rx_pulse_p3            (w_osm_req_rx_pulse_p3_osm2hcp  ),
.i_osm_resp_tx_pulse_p3           (w_osm_resp_tx_pulse_p3_osm2hcp ),
.i_osm_req_rx_pulse_p4            (1'b0),//(w_osm_req_rx_pulse_p4_osm2hcp  ),
.i_osm_resp_tx_pulse_p4           (1'b0),//(w_osm_resp_tx_pulse_p4_osm2hcp ),
.i_osm_req_rx_pulse_p5            (1'b0),//(w_osm_req_rx_pulse_p5_osm2hcp  ),
.i_osm_resp_tx_pulse_p5           (1'b0),//(w_osm_resp_tx_pulse_p5_osm2hcp ),
.i_osm_req_rx_pulse_p6            (1'b0),//(w_osm_req_rx_pulse_p6_osm2hcp  ),
.i_osm_resp_tx_pulse_p6           (1'b0),//(w_osm_resp_tx_pulse_p6_osm2hcp ),
.i_osm_req_rx_pulse_p7            (1'b0),//(w_osm_req_rx_pulse_p7_osm2hcp  ),
.i_osm_resp_tx_pulse_p7           (1'b0),//(w_osm_resp_tx_pulse_p7_osm2hcp ),
.i_osm_req_rx_pulse_p8            (1'b0),//(w_osm_req_rx_pulse_p8_osm2hcp  ),
.i_osm_resp_tx_pulse_p8           (1'b0),//(w_osm_resp_tx_pulse_p8_osm2hcp ),
.i_osm_req_rx_pulse_p9            (1'b0),//(w_osm_req_rx_pulse_p9_osm2hcp  ),
.i_osm_resp_tx_pulse_p9           (1'b0),//(w_osm_resp_tx_pulse_p9_osm2hcp ),
.i_osm_req_rx_pulse_p10           (1'b0),//(w_osm_req_rx_pulse_p10_osm2hcp ),
.i_osm_resp_tx_pulse_p10          (1'b0),//(w_osm_resp_tx_pulse_p10_osm2hcp),
.i_osm_req_rx_pulse_p11           (1'b0),//(w_osm_req_rx_pulse_p11_osm2hcp ),
.i_osm_resp_tx_pulse_p11          (1'b0),//(w_osm_resp_tx_pulse_p11_osm2hcp),
.i_osm_req_rx_pulse_p12           (1'b0),//(w_osm_req_rx_pulse_p12_osm2hcp ),
.i_osm_resp_tx_pulse_p12          (1'b0),//(w_osm_resp_tx_pulse_p12_osm2hcp),
.i_osm_req_rx_pulse_p13           (1'b0),//(w_osm_req_rx_pulse_p13_osm2hcp ),
.i_osm_resp_tx_pulse_p13          (1'b0),//(w_osm_resp_tx_pulse_p13_osm2hcp),
.i_osm_req_rx_pulse_p14           (1'b0),//(w_osm_req_rx_pulse_p14_osm2hcp ),
.i_osm_resp_tx_pulse_p14          (1'b0),//(w_osm_resp_tx_pulse_p14_osm2hcp),
.i_osm_req_rx_pulse_p15           (1'b0),//(w_osm_req_rx_pulse_p15_osm2hcp ),
.i_osm_resp_tx_pulse_p15          (1'b0),//(w_osm_resp_tx_pulse_p15_osm2hcp),
.i_osm_req_rx_pulse_p16           (1'b0),//(w_osm_req_rx_pulse_p16_osm2hcp ),
.i_osm_resp_tx_pulse_p16          (1'b0),//(w_osm_resp_tx_pulse_p16_osm2hcp),
.i_osm_req_rx_pulse_p17           (1'b0),//(w_osm_req_rx_pulse_p17_osm2hcp ),
.i_osm_resp_tx_pulse_p17          (1'b0),//(w_osm_resp_tx_pulse_p17_osm2hcp),
.i_osm_req_rx_pulse_p18           (1'b0),//(w_osm_req_rx_pulse_p18_osm2hcp ),
.i_osm_resp_tx_pulse_p18          (1'b0),//(w_osm_resp_tx_pulse_p18_osm2hcp),
.i_osm_req_rx_pulse_p19           (1'b0),//(w_osm_req_rx_pulse_p19_osm2hcp ),
.i_osm_resp_tx_pulse_p19          (1'b0),//(w_osm_resp_tx_pulse_p19_osm2hcp),
.i_osm_req_rx_pulse_p20           (1'b0),//(w_osm_req_rx_pulse_p20_osm2hcp ),
.i_osm_resp_tx_pulse_p20          (1'b0),//(w_osm_resp_tx_pulse_p20_osm2hcp),
.i_osm_req_rx_pulse_p21           (1'b0),//(w_osm_req_rx_pulse_p21_osm2hcp ),
.i_osm_resp_tx_pulse_p21          (1'b0),//(w_osm_resp_tx_pulse_p21_osm2hcp),
.i_osm_req_rx_pulse_p22           (1'b0),//(w_osm_req_rx_pulse_p22_osm2hcp ),
.i_osm_resp_tx_pulse_p22          (1'b0),//(w_osm_resp_tx_pulse_p22_osm2hcp),
.i_osm_req_rx_pulse_p23           (1'b0),//(w_osm_req_rx_pulse_p23_osm2hcp ),
.i_osm_resp_tx_pulse_p23          (1'b0),//(w_osm_resp_tx_pulse_p23_osm2hcp),
.i_osm_req_rx_pulse_p24           (1'b0),//(w_osm_req_rx_pulse_p24_osm2hcp ),
.i_osm_resp_tx_pulse_p24          (1'b0),//(w_osm_resp_tx_pulse_p24_osm2hcp),
.i_osm_req_rx_pulse_p25           (1'b0),//(w_osm_req_rx_pulse_p25_osm2hcp ),
.i_osm_resp_tx_pulse_p25          (1'b0),//(w_osm_resp_tx_pulse_p25_osm2hcp),
.i_osm_req_rx_pulse_p26           (1'b0),//(w_osm_req_rx_pulse_p26_osm2hcp ),
.i_osm_resp_tx_pulse_p26          (1'b0),//(w_osm_resp_tx_pulse_p26_osm2hcp),
.i_osm_req_rx_pulse_p27           (1'b0),//(w_osm_req_rx_pulse_p27_osm2hcp ),
.i_osm_resp_tx_pulse_p27          (1'b0),//(w_osm_resp_tx_pulse_p27_osm2hcp),
.i_osm_req_rx_pulse_p28           (1'b0),//(w_osm_req_rx_pulse_p28_osm2hcp ),
.i_osm_resp_tx_pulse_p28          (1'b0),//(w_osm_resp_tx_pulse_p28_osm2hcp),
.i_osm_req_rx_pulse_p29           (1'b0),//(w_osm_req_rx_pulse_p29_osm2hcp ),
.i_osm_resp_tx_pulse_p29          (1'b0),//(w_osm_resp_tx_pulse_p29_osm2hcp),
.i_osm_req_rx_pulse_p30           (1'b0),//(w_osm_req_rx_pulse_p30_osm2hcp ),
.i_osm_resp_tx_pulse_p30          (1'b0),//(w_osm_resp_tx_pulse_p30_osm2hcp),
.i_osm_req_rx_pulse_p31           (1'b0),//(w_osm_req_rx_pulse_p31_osm2hcp ),
.i_osm_resp_tx_pulse_p31          (1'b0) //(w_osm_resp_tx_pulse_p31_osm2hcp)   
);  

mbus_hub mbus_hub_inst
(
        .i_clk                        (i_core_clk                ),
        .i_rst_n                      (w_core_rst_n              ),
                                                                 
        .iv_command                   (wv_command_hcp2hub        ),
	    .i_command_wr                 (w_command_wr_hcp2hub      ),
        .ov_command_ack               (wv_command_ack_hub2hcp    ),
        .o_command_ack_wr             (w_command_ack_wr_hub2hcp  ), 
                                                                 
        .iv_command_ack_tse           (wv_command_tse2hub        ),
	    .i_command_ack_wr_tse         (w_command_wr_tse2hub      ),
        .ov_command_tse               (wv_command_hub2tse        ),
        .o_command_wr_tse             (w_command_wr_hub2tse      ),
                                                                 
        .iv_command_ack_tau           (64'b0),//(wv_command_tau2hub        ),
	    .i_command_ack_wr_tau         (1'b0 ),//(w_command_wr_tau2hub      ),
        .ov_command_tau               (     ),
        .o_command_wr_tau             (     ),           
      
        .iv_command_ack_osm_0         (wv_command_osm2hub_0      ),
	    .i_command_ack_wr_osm_0       (w_command_wr_osm2hub_0    ),
        .ov_command_osm_0             (wv_command_hub2osm_0      ),
        .o_command_wr_osm_0           (w_command_wr_hub2osm_0    ),
 
        .iv_command_ack_osm_1         (wv_command_osm2hub_1      ),
	    .i_command_ack_wr_osm_1       (w_command_wr_osm2hub_1    ),
        .ov_command_osm_1             (wv_command_hub2osm_1      ),
        .o_command_wr_osm_1           (w_command_wr_hub2osm_1    ),
                            
        .iv_command_ack_osm_2         (wv_command_osm2hub_2      ),
	    .i_command_ack_wr_osm_2       (w_command_wr_osm2hub_2    ),
        .ov_command_osm_2             (wv_command_hub2osm_2      ),
        .o_command_wr_osm_2           (w_command_wr_hub2osm_2    ), 
                           
        .iv_command_ack_osm_3         (wv_command_osm2hub_3      ),
	    .i_command_ack_wr_osm_3       (w_command_wr_osm2hub_3    ),
        .ov_command_osm_3             (wv_command_hub2osm_3      ),
        .o_command_wr_osm_3           (w_command_wr_hub2osm_3    ),
                             
        .iv_command_ack_osm_4         (64'b0     ),
	    .i_command_ack_wr_osm_4       (1'b0      ),
        .ov_command_osm_4             (          ),
        .o_command_wr_osm_4           (          ), 
                           
        .iv_command_ack_osm_5         (64'b0     ),
	    .i_command_ack_wr_osm_5       (1'b0      ),
        .ov_command_osm_5             (          ),
        .o_command_wr_osm_5           (          ), 
                           
        .iv_command_ack_osm_6         (64'b0     ),
	    .i_command_ack_wr_osm_6       (1'b0      ),
        .ov_command_osm_6             (          ),
        .o_command_wr_osm_6           (          ), 
                        
        .iv_command_ack_osm_7         (64'b0     ),
	    .i_command_ack_wr_osm_7       (1'b0      ),
        .ov_command_osm_7             (          ),
        .o_command_wr_osm_7           (          )     
);

opensync_mac opensync_mac_inst(
.i_clk                    (i_core_clk     ),
.i_rst_n                  (w_core_rst_n   ),

.iv_hcp_mid               (wv_hcp_mid_hcp2tse       ),                          
.i_local_cnt_rst          (w_local_cnt_rst_hcp2osm  ),
.i_tsn_or_tte             (w_tsn_or_tte_hcp2osm     ),

.iv_command_osm_0         (wv_command_hub2osm_0      ),
.i_command_wr_osm_0       (w_command_wr_hub2osm_0    ),
.ov_command_ack_osm_0     (wv_command_osm2hub_0      ),
.o_command_ack_wr_osm_0   (w_command_wr_osm2hub_0    ),

.iv_command_osm_1         (wv_command_hub2osm_1      ),
.i_command_wr_osm_1       (w_command_wr_hub2osm_1    ),
.ov_command_ack_osm_1     (wv_command_osm2hub_1      ),
.o_command_ack_wr_osm_1   (w_command_wr_osm2hub_1    ),
                    
.iv_command_osm_2         (wv_command_hub2osm_2      ),
.i_command_wr_osm_2       (w_command_wr_hub2osm_2    ),
.ov_command_ack_osm_2     (wv_command_osm2hub_2      ),
.o_command_ack_wr_osm_2   (w_command_wr_osm2hub_2    ), 
                   
.iv_command_osm_3         (wv_command_hub2osm_3      ),
.i_command_wr_osm_3       (w_command_wr_hub2osm_3    ),
.ov_command_ack_osm_3     (wv_command_osm2hub_3      ),
.o_command_ack_wr_osm_3   (w_command_wr_osm2hub_3    ),
                     
.iv_command_osm_4         (64'b0    ),
.i_command_wr_osm_4       (1'b0     ),
.ov_command_ack_osm_4     (         ),
.o_command_ack_wr_osm_4   (         ), 
                   
.iv_command_osm_5         (64'b0    ),
.i_command_wr_osm_5       (1'b0     ),
.ov_command_ack_osm_5     (         ),
.o_command_ack_wr_osm_5   (         ), 
                   
.iv_command_osm_6         (64'b0    ),
.i_command_wr_osm_6       (1'b0     ),
.ov_command_ack_osm_6     (         ),
.o_command_ack_wr_osm_6   (         ), 
                
.iv_command_osm_7         (64'b0    ),
.i_command_wr_osm_7       (1'b0     ),
.ov_command_ack_osm_7     (         ),
.o_command_ack_wr_osm_7   (         ),  
//p0
.i_gmii_clk_p0       (i_gmii_rxclk_p0),                
.i_gmii_rst_n_p0     (w_gmii_rst_n_p0),                                                           
.i_gmii_rx_dv_p0     (i_gmii_rxdv_p0 ),         
.i_gmii_rx_er_p0     (i_gmii_rxer_p0 ),        
.iv_gmii_rxd_p0      (iv_gmii_rxd_p0 ),          
.o_gmii_tx_en_p0     (o_gmii_txen_p0 ),           
.o_gmii_tx_er_p0     (o_gmii_txer_p0 ),           
.ov_gmii_txd_p0      (ov_gmii_txd_p0 ),
    
.i_data_wr_p0        (w_data_wr_p0_hcp2osm      ), 
.iv_data_p0          (wv_data_p0_hcp2osm        ), 
.o_data_ready_p0     (                          ), 
.o_data_wr_p0        (w_data_wr_p0_osm2hcp      ), 
.ov_data_p0          (wv_data_p0_osm2hcp        ),
//p1 
.i_gmii_clk_p1       (i_gmii_rxclk_p1           ),                
.i_gmii_rst_n_p1     (w_gmii_rst_n_p1           ), 
                                                          
.i_gmii_rx_dv_p1     (i_gmii_rxdv_p1            ),                       
.i_gmii_rx_er_p1     (i_gmii_rxer_p1            ),                      
.iv_gmii_rxd_p1      (iv_gmii_rxd_p1            ),                       
.o_gmii_tx_en_p1     (o_gmii_txen_p1            ),           
.o_gmii_tx_er_p1     (o_gmii_txer_p1            ),          
.ov_gmii_txd_p1      (ov_gmii_txd_p1            ),          
                                                
.i_data_wr_p1        (w_data_wr_p1_iop2osm      ),         
.iv_data_p1          (wv_data_p1_iop2osm        ),                      
.o_data_ready_p1     (w_data_ready_p1_osm2iop   ),                      
.o_data_wr_p1        (w_data_wr_p1_osm2iip      ),                      
.ov_data_p1          (wv_data_p1_osm2iip        ),         
//p2                                   
.i_gmii_clk_p2       (i_gmii_rxclk_p2           ),                
.i_gmii_rst_n_p2     (w_gmii_rst_n_p2           ),     
                                                                          
.i_gmii_rx_dv_p2     (i_gmii_rxdv_p2            ),         
.i_gmii_rx_er_p2     (i_gmii_rxer_p2            ),        
.iv_gmii_rxd_p2      (iv_gmii_rxd_p2            ),          
.o_gmii_tx_en_p2     (o_gmii_txen_p2            ),           
.o_gmii_tx_er_p2     (o_gmii_txer_p2            ),           
.ov_gmii_txd_p2      (ov_gmii_txd_p2            ),
                                                
.i_data_wr_p2        (w_data_wr_p2_iop2osm      ), 
.iv_data_p2          (wv_data_p2_iop2osm        ), 
.o_data_ready_p2     (w_data_ready_p2_osm2iop   ),
.o_data_wr_p2        (w_data_wr_p2_osm2iip      ), 
.ov_data_p2          (wv_data_p2_osm2iip        ) ,
//p3    
.i_gmii_clk_p3       (i_gmii_rxclk_p3           ),   
.i_gmii_rst_n_p3     (w_gmii_rst_n_p3           ),
                                                                            
.i_gmii_rx_dv_p3     (i_gmii_rxdv_p3            ),         
.i_gmii_rx_er_p3     (i_gmii_rxer_p3            ),        
.iv_gmii_rxd_p3      (iv_gmii_rxd_p3            ),           
.o_gmii_tx_en_p3     (o_gmii_txen_p3            ),            
.o_gmii_tx_er_p3     (o_gmii_txer_p3            ),  
.ov_gmii_txd_p3      (ov_gmii_txd_p3            ),
                                                
.i_data_wr_p3        (w_data_wr_p3_iop2osm      ), 
.iv_data_p3          (wv_data_p3_iop2osm        ), 
.o_data_ready_p3     (w_data_ready_p3_osm2iop   ), 
.o_data_wr_p3        (w_data_wr_p3_osm2iip      ), 
.ov_data_p3          (wv_data_p3_osm2iip        ),
//p4 
.i_gmii_clk_p4       (i_core_clk),    
.i_gmii_rst_n_p4     (1'b0      ), 
                                                            
.i_gmii_rx_dv_p4     (1'b0 ),          
.i_gmii_rx_er_p4     (1'b0 ),        
.iv_gmii_rxd_p4      (8'b0 ),            
.o_gmii_tx_en_p4     (     ),             
.o_gmii_tx_er_p4     (     ),   
.ov_gmii_txd_p4      (     ),
                     
.i_data_wr_p4        (1'b0 ),  
.iv_data_p4          (8'b0 ),  
.o_data_ready_p4     (     ), 
.o_data_wr_p4        (     ),  
.ov_data_p4          (     ),
//p5
.i_gmii_clk_p5       (i_core_clk),    
.i_gmii_rst_n_p5     (1'b0      ),  
                                                           
.i_gmii_rx_dv_p5     (1'b0 ),          
.i_gmii_rx_er_p5     (1'b0 ),        
.iv_gmii_rxd_p5      (8'b0 ),            
.o_gmii_tx_en_p5     (     ),             
.o_gmii_tx_er_p5     (     ),   
.ov_gmii_txd_p5      (     ),
                     
.i_data_wr_p5        (1'b0 ),  
.iv_data_p5          (8'b0 ),
.o_data_ready_p5     (     ),   
.o_data_wr_p5        (     ),  
.ov_data_p5          (     ),
//p6
.i_gmii_clk_p6       (i_core_clk),   
.i_gmii_rst_n_p6     (1'b0      ),  
                                                          
.i_gmii_rx_dv_p6     (1'b0 ),         
.i_gmii_rx_er_p6     (1'b0 ),        
.iv_gmii_rxd_p6      (8'b0 ),           
.o_gmii_tx_en_p6     (     ),            
.o_gmii_tx_er_p6     (     ),  
.ov_gmii_txd_p6      (     ),
                     
.i_data_wr_p6        (1'b0 ), 
.iv_data_p6          (8'b0 ),
.o_data_ready_p6     (     ),  
.o_data_wr_p6        (     ), 
.ov_data_p6          (     ),
//p7
.i_gmii_clk_p7       (i_core_clk),   
.i_gmii_rst_n_p7     (1'b0      ),  
                                                          
.i_gmii_rx_dv_p7     (1'b0 ),         
.i_gmii_rx_er_p7     (1'b0 ),        
.iv_gmii_rxd_p7      (8'b0 ),           
.o_gmii_tx_en_p7     (     ),            
.o_gmii_tx_er_p7     (     ),  
.ov_gmii_txd_p7      (     ),
                     
.i_data_wr_p7        (1'b0 ), 
.iv_data_p7          (8'b0 ),
.o_data_ready_p7     (     ),  
.o_data_wr_p7        (     ), 
.ov_data_p7          (     ),

.o_osm_req_rx_pulse_p0    (w_osm_req_rx_pulse_p0_osm2hcp  ),    
.o_osm_resp_rx_pulse_p0   (w_osm_resp_rx_pulse_p0_osm2hcp ),    
.o_osm_req_tx_pulse_p0    (w_osm_req_tx_pulse_p0_osm2hcp  ),    
.o_osm_resp_tx_pulse_p0   (w_osm_resp_tx_pulse_p0_osm2hcp ),    
     
.o_osm_req_rx_pulse_p1    (w_osm_req_rx_pulse_p1_osm2hcp  ),     
.o_osm_resp_rx_pulse_p1   (w_osm_resp_rx_pulse_p1_osm2hcp ),     
.o_osm_req_tx_pulse_p1    (w_osm_req_tx_pulse_p1_osm2hcp  ),     
.o_osm_resp_tx_pulse_p1   (w_osm_resp_tx_pulse_p1_osm2hcp ),     
     
.o_osm_req_rx_pulse_p2    (w_osm_req_rx_pulse_p2_osm2hcp  ),     
.o_osm_resp_rx_pulse_p2   (w_osm_resp_rx_pulse_p2_osm2hcp ),     
.o_osm_req_tx_pulse_p2    (w_osm_req_tx_pulse_p2_osm2hcp  ),     
.o_osm_resp_tx_pulse_p2   (w_osm_resp_tx_pulse_p2_osm2hcp ),     
     
.o_osm_req_rx_pulse_p3    (w_osm_req_rx_pulse_p3_osm2hcp  ),     
.o_osm_resp_rx_pulse_p3   (w_osm_resp_rx_pulse_p3_osm2hcp ),
.o_osm_req_tx_pulse_p3    (w_osm_req_tx_pulse_p3_osm2hcp  ),
.o_osm_resp_tx_pulse_p3   (w_osm_resp_tx_pulse_p3_osm2hcp ),
 
.o_osm_req_rx_pulse_p4    ( ),
.o_osm_resp_rx_pulse_p4   ( ),
.o_osm_req_tx_pulse_p4    ( ),
.o_osm_resp_tx_pulse_p4   ( ),
                            
.o_osm_req_rx_pulse_p5    ( ),
.o_osm_resp_rx_pulse_p5   ( ),
.o_osm_req_tx_pulse_p5    ( ),
.o_osm_resp_tx_pulse_p5   ( ),
                            
.o_osm_req_rx_pulse_p6    ( ),
.o_osm_resp_rx_pulse_p6   ( ),
.o_osm_req_tx_pulse_p6    ( ),
.o_osm_resp_tx_pulse_p6   ( ),
                            
.o_osm_req_rx_pulse_p7    ( ),
.o_osm_resp_rx_pulse_p7   ( ),
.o_osm_req_tx_pulse_p7    ( ),
.o_osm_resp_tx_pulse_p7   ( ) 
);

reset_sync core_reset_sync(
.i_clk          (i_core_clk),
.i_rst_n        (i_rst_n),
.o_rst_n_sync   (w_core_rst_n)   
);

reset_sync gmii_p0_reset_sync(
.i_clk          (i_gmii_rxclk_p0),
.i_rst_n        (i_rst_n),
.o_rst_n_sync   (w_gmii_rst_n_p0)   
);

reset_sync gmii_p1_reset_sync(
.i_clk          (i_gmii_rxclk_p1),
.i_rst_n        (i_rst_n),
.o_rst_n_sync   (w_gmii_rst_n_p1)   
);

reset_sync gmii_p2_reset_sync(
.i_clk          (i_gmii_rxclk_p2),
.i_rst_n        (i_rst_n),
.o_rst_n_sync   (w_gmii_rst_n_p2)   
);

reset_sync gmii_p3_reset_sync(
.i_clk          (i_gmii_rxclk_p3),
.i_rst_n        (i_rst_n),
.o_rst_n_sync   (w_gmii_rst_n_p3)   
);

command_parse_and_encapsulate_tst command_parse_and_encapsulate_tst_inst(
.i_clk		      (i_core_clk                 ),
.i_rst_n	      (w_core_rst_n               ),
                                         
.iv_command       (wv_command_hub2tse    ), 
.i_command_wr     (w_command_wr_hub2tse  ),                
                                                         
.ov_addr          (wv_addr_cit2all       ),            
.ov_wdata         (wv_wdata_cit2all      ),          
.o_wr_grm         (w_wr_cit2grm          ),
.o_rd_grm         (w_rd_cit2grm          ),	                                                                                                                                                                                           
.i_wr_grm         (w_wr_grm2cit          ),
.iv_addr_grm      (wv_addr_grm2cit       ),
.iv_rdata_grm     (wv_rdata_grm2cit      ),
                                                                                                                
.ov_command_ack   (wv_command_tse2hub    ),
.o_command_ack_wr (w_command_wr_tse2hub  )         
);

global_registers_management global_registers_management_inst(
.i_clk                         (i_core_clk                  ),                
.i_rst_n                       (w_core_rst_n                ),      
                                                       
.iv_addr                       (wv_addr_cit2all        ),         
.iv_wdata                      (wv_wdata_cit2all       ),
.i_wr                          (w_wr_cit2grm           ),      
.i_rd                          (w_rd_cit2grm           ),                                                                                      
.o_wr                          (w_wr_grm2cit           ),      
.ov_addr                       (wv_addr_grm2cit        ),      
.ov_rdata                      (wv_rdata_grm2cit       ),      

.o_qbv_or_qch                  (  ),          
.ov_time_slot_length           (wv_time_slot_length    ),   
.ov_port_mode                  (  ),          
.ov_schedule_period            (wv_schedule_period     )     
);

timing timing_inst
(
    .i_clk       (i_core_clk     ),
    .i_rst_n     (w_core_rst_n   ),
               
    .ov_local_cnt(wv_local_cnt_tim2other  )
);

interface_input_process interface_input_process_p1_inst(
.i_clk                  (i_core_clk                 ),
.i_rst_n                (w_core_rst_n               ),
                                                    
.iv_local_cnt           (wv_local_cnt_tim2other     ),
.iv_syn_clk             (wv_syn_clk_hcp2other[63:0] ),

.i_data_wr              (w_data_wr_p1_osm2iip          ),      
.iv_data                (wv_data_p1_osm2iip            ),	   
                                                                        
.ov_data                (wv_data_iip12um               ),                                 
.o_data_wr              (w_data_wr_iip12um             ),                         
.o_fifo_overflow_pulse  (w_fifo_overflow_pulse_iip12um ),                
.o_fifo_underflow_pulse (w_fifo_underflow_pulse_iip12um)                  
);
interface_input_process interface_input_process_p2_inst(
.i_clk                  (i_core_clk),
.i_rst_n                (w_core_rst_n),

.iv_local_cnt           (wv_local_cnt_tim2other),
.iv_syn_clk             (wv_syn_clk_hcp2other[63:0] ),

.i_data_wr              (w_data_wr_p2_osm2iip    ),
.iv_data                (wv_data_p2_osm2iip      ),   

.ov_data                (wv_data_iip22um               ),
.o_data_wr              (w_data_wr_iip22um             ),
.o_fifo_overflow_pulse  (w_fifo_overflow_pulse_iip22um ),
.o_fifo_underflow_pulse (w_fifo_underflow_pulse_iip22um)
);
interface_input_process interface_input_process_p3_inst(
.i_clk                  (i_core_clk),
.i_rst_n                (w_core_rst_n),

.iv_local_cnt           (wv_local_cnt_tim2other),
.iv_syn_clk             (wv_syn_clk_hcp2other[63:0] ),

.i_data_wr              (w_data_wr_p3_osm2iip),
.iv_data                (wv_data_p3_osm2iip  ),  

.ov_data                (wv_data_iip32um               ),
.o_data_wr              (w_data_wr_iip32um             ),
.o_fifo_overflow_pulse  (w_fifo_overflow_pulse_iip32um ),
.o_fifo_underflow_pulse (w_fifo_underflow_pulse_iip32um)
);

time_slot_calculation time_slot_calculation_inst
(
.i_clk                  (i_core_clk),
.i_rst_n                (w_core_rst_n),

.i_cycle_start          (o_cycle_start),
.iv_time_slot_length    (wv_time_slot_length),
.iv_slot_period         (wv_schedule_period ),

.ov_time_slot           (wv_time_slot      ),
.o_time_slot_switch     (w_time_slot_switch)       
);

um um_inst(
.clk                    (i_core_clk),
.rst_n                  (w_core_rst_n), 
    
.i_time_slot_switch     (w_time_slot_switch),
.iv_time_slot           (wv_time_slot), 
.iv_syn_clk             (wv_syn_clk_hcp2other[63:0] ),
.i_cycle_start          (o_cycle_start),
.iv_time_slot_period    (wv_schedule_period),
.iv_cfg_finish          (ov_cfg_finish),    
// port12um
.iv_data_wr_p1          (w_data_wr_iip12um),
.iv_data_p1             (wv_data_iip12um),

.ov_data_p1             (wv_data_um2p1),
.o_data_wr_p1           (w_data_um2p1_wr),
.iv_fifo_usedw_p1       (wv_fifo_usedw_p12um),    
// port22um 
.iv_data_wr_p2          (w_data_wr_iip22um),
.iv_data_p2             (wv_data_iip22um),

.ov_data_p2             (wv_data_um2p2),
.o_data_wr_p2           (w_data_um2p2_wr),
.iv_fifo_usedw_p2       (wv_fifo_usedw_p22um),   
// port32um
.iv_data_wr_p3          (w_data_wr_iip32um),
.iv_data_p3             (wv_data_iip32um),

.ov_data_p3             (wv_data_um2p3),
.o_data_wr_p3           (w_data_um2p3_wr),
.iv_fifo_usedw_p3       (wv_fifo_usedw_p32um)
);

interface_output_process interface_output_process_p1_inst
(
.i_clk                  (i_core_clk  ),
.i_rst_n                (w_core_rst_n),

.iv_local_clk           (wv_local_cnt_tim2other     ),
.iv_syn_clk             (wv_syn_clk_hcp2other[63:0] ),
.iv_data                (wv_data_um2p1              ),
.i_data_wr              (w_data_um2p1_wr            ),
.ov_fifo_usedw          (wv_fifo_usedw_p12um        ),        

.ov_data                (wv_data_p1_iop2osm     ),     
.o_data_wr              (w_data_wr_p1_iop2osm   ),     
.i_data_ready           (w_data_ready_p1_osm2iop)
);

interface_output_process interface_output_process_p2_inst
(
.i_clk                  (i_core_clk                 ),
.i_rst_n                (w_core_rst_n               ),

.iv_local_clk           (wv_local_cnt_tim2other     ),
.iv_syn_clk             (wv_syn_clk_hcp2other[63:0] ),
.iv_data                (wv_data_um2p2              ),
.i_data_wr              (w_data_um2p2_wr            ),
.ov_fifo_usedw          (wv_fifo_usedw_p22um        ),        
        
.ov_data                (wv_data_p2_iop2osm     ),
.o_data_wr              (w_data_wr_p2_iop2osm   ),
.i_data_ready           (w_data_ready_p2_osm2iop)
);

interface_output_process interface_output_process_p3_inst
(
.i_clk                  (i_core_clk),
.i_rst_n                (w_core_rst_n),

.iv_local_clk           (wv_local_cnt_tim2other),
.iv_syn_clk             (wv_syn_clk_hcp2other[63:0] ),
.iv_data                (wv_data_um2p3),
.i_data_wr              (w_data_um2p3_wr),
.ov_fifo_usedw          (wv_fifo_usedw_p32um),        
        
.ov_data                (wv_data_p3_iop2osm     ),
.o_data_wr              (w_data_wr_p3_iop2osm   ),
.i_data_ready           (w_data_ready_p3_osm2iop)
);
endmodule